The present invention relates to a synchronous semiconductor device. Moreover, the present invention relates to a timing control for receiving a clock signal for synchronization.
For a high speed operation of a synchronous semiconductor device, a fabrication process is decided as a target process based on a specification requested by a customer. Then, even if the target process fluctuates, operations are assured in the range of operational conditions for evaluating the specification. To assure the operations, operational timing between internal circuits of the semiconductor device is set. However, to assure the operation for process fluctuation, the above timing is set to the slowest timing which can be generated. Thereby, the high-speed operation which was originally designed for a semiconductor device may be sacrificed.
This is because the optimum operational timing between internal circuits which was originally designed by considering fluctuations in the fabrication conditions of the fabrication process of a semiconductor device is not an optimum timing for each semiconductor device.